Long retention of charge is important to the success of a DRAM cell design. Among the mechanisms known to be responsible for charge leakage, several are enhanced by the charge stored in the capacitor itself. For these mechanisms, discussed in more detail below, the capacitor gates its own leakage.
In connection with the following discussion of capacitor charge leakage in conventional trench memory cells, reference should be made to the prior art trench memory cell illustrated in FIG. 1. The cell includes CMOS transistor 7 located in n-well 19 formed in p- epitaxial silicon (epi) layer 13 grown on p+ silicon substrate 14. Transistor 7 has diffusion 8 connected through surface strap 9 to capacitor 10 formed in trench 11. Because of its direct connection to a capacitor electrode, in this case inner electrode 17 of capacitor 10, this transistor diffusion 8 is known as the node diffusion. Trench 11 is lined with a relatively thin dielectric layer 15 along a middle and bottom sidewall portion and a relatively thick dielectric layer 16 along a top sidewall portion. Inner electrode 17 of trench capacitor 10 is formed from p+ doped polycrystalline silicon (polysilicon) and fills the portions of trench 11 not occupied by dielectric layers 15 and 16. The outer electrode of capacitor 10 is formed from p+ substrate 14 surrounding trench 11. The potential of outer electrode 14 typically is held fixed while the potential of electrode 17 varies under the control of transistor 7. The varying electrode, in this case inner electrode 17, is also called the storage node.
One mechanism by which the capacitor gates its own leakage is identified as the gated diode mechanism. As will be discussed in more detail hereinafter, a gate disposed along the junction of a diode causes depletion of charge on one electrode of the diode when the gate is held at a high voltage and causes depletion of charge on the other electrode when the gate is held low. Charges generated within the depletion region on either side of the junction are swept across the junction and are a source of leakage current that limits the retention time of the cell. Generation of charge in the depletion region of a diode electrode depends on factors including the doping level and the presence of defects in the silicon of the depletion region.
There are at least two gated diodes along the periphery of the prior art trench capacitor illustrated in FIG. 1. The first gated diode is formed from node diffusion 8 and n-well 19. The junction of the diode exists at the interface of diffusion 8 and n-well 19 and adjoins dielectric layer 16. Both electrodes of the diode are effected by the variation of charge on capacitor. electrode 17 which serves as the gate of the diode. As the charge on electrode 17 changes, either the lightly doped n-well 19 side or the heavily doped node diffusion 8 side of the diode is depleted. Electron-hole pairs generated within the depletion regions-are swept across the junction by the diode built-in potential and discharge the capacitor by way of the node diffusion and surface strap.
Another problem caused by the gated diode mechanism is high chip standby current. Standby current is the current flowing through the chip when nothing else is happening. The result of higher standby current is faster draining of batteries that may be the power supply for the memory chips. Standby current is increased when the second of the above-mentioned gated diodes experiences gated diode leakage. This second gated diode is formed at the boundary between p- epi layer 13 and lightly doped n-well 19 and adjoins dielectric layer 16. Both electrodes 13 and 19 of the diode are effected by the variation of charge on electrode 17 which serves as the gate of the diode. As the charge on electrode 17 changes, either the p- layer 13 side or the n- well 19 side of the diode is depleted. Electron-hole pairs generated within the depletion regions are swept across the junction by the diode built-in potential and are collected by power supply contacts.
Another leakage mechanism gated by the capacitor is lateral punch-through between node diffusions of adjacent cells. Punch through current between a bode diffusion held at a high electrical potential, typically about 3.3 Volts, and an adjacent node diffusion held at a low electrical potential, typically about 0 Volts, is substantially increased because the node electrode gates the n-well. Since the n-well is typically held at a potential 1 volt above the power supply voltage (VDD), or about 4.6 Volts, the n-well adjacent each of the two trench capacitors is depleted by the gating of the node electrode of the capacitor. The area for punch-through current flow includes the area of these depletion regions as well as the area of the two node diffusions. If the depletion regions of the adjacent trenches overlap, punch-through currents flow, and charges are swept between the nodes, discharging one of the capacitors. The spacing between trench cells is expected ultimately to be limited by punch-through between capacitor gate induced depletion layers if means to reduce the capacitor gating is not implemented.
Another mechanism by which the capacitor gates its own leakage, also described with reference to FIG. 1, involves the gating of unwanted vertical and horizontal parasitic transistors by the charge stored on electrode 17. A vertical parasitic transistor can be formed between node diffusion 8 and p- epi layer 13. A horizontal parasitic capacitor can be formed between node diffusion 8 of one transistor and the node diffusion of a neighboring cell (not shown). A low voltage on the capacitor electrode depletes or inverts the doping on the lightly doped semiconductor between the two diffusions. Sub-threshold currents between the diffusions, along with the gated diode currents, may be sufficient to seriously degrade the retention time of memory cells.
The trench capacitor can also serve as an alternate gate between the diffusions of the transfer transistor in cell designs in which the gate of the transistor crosses over the trench capacitor. If, in this design, the voltage on the node electrode in the trench depletes the lightly doped region between the diffusions of the transistor, sub-threshold currents can decrease retention time. In addition, in this design a corner transistor in parallel with the bulk transfer device located at the intersection of the transistor and the trench capacitor is found to have a significantly lower threshold voltage than the bulk device, and therefore, substantially higher leakage.
Moreover, depletion along the trench sidewall due to charge on the capacitor diminishes well resistance, thereby decreasing the speed of the DRAM cell and increasing circuit noise and latch-up sensitivity.
Thus, it is desirable to reduce the field strength of the capacitor storage electrode gating the diodes and the n-well. Two methods have been proposed in the prior art for reducing this field strength: (1) thick dielectric collars and (2) conducting field shields. In commonly assigned U.S. Pat. No. 4,801,988, issued to Kenney, a structure and process is described for making a thick dielectric collar along an upper sidewall portion of a trench capacitor, for example, collar 16 illustrated in FIG. 1. A sufficiently thick dielectric collar is effective at lowering all, the electric fields in the transfer device region, thereby (1) minimizing the width of depletion regions in adjacent layers and the magnitude of charge generated therein and (2) raising the threshold voltage for parasitic transistors. However, a thick collar has two problems: first, a thick collar provides an extended length within the trench not contributing to capacitance, and second, its girth conflicts with the need to construct ever more densely packed arrays.
Japanese Patent 2-77155 to Goto and Suzuki and U.S. Pat. No. 4,918,502 to Kaga et al. (the '502 patent), disclose trench memory cells having field shields electrically connected to the substrate at the trench bottom. These field shields are used in place of a thick dielectric collar, thereby avoiding the reduction of trench capacitance that occurs by using a thick dielectric collar. The field shield's substrate contact reduces one of the gated diode leakage problems, the one contributing to standby current, by eliminating the potential difference between the field shield and the substrate. However, it is believed that this structure intensifies the depletion of the n-well. For example, for a p- array cell design, the substrate is typically held at ground potential while the n-well is held at a potential 1 volt above the power supply voltage, which is typically 3.6 volts. Thus, the n-well will be depleted by the field shield gate, which is 4.6 volts lower than the n-well potential, and the structure will continue to generate leakage from the storage node because of vertical and horizontal parasitic transistors and gated diode currents from the node diode. The '502 patent illustrates contact between the field shield and a buried plate at the bottom of the trench for an n array cell design. Contact to a buried plate does not solve the above mentioned problem, since to avoid increasing standby current the n+ buried plate potential can be no lower than the p- substrate potential.
U.S. Pat. No. 5,041,887 to Kumagai et al. (the '887 patent), U.S. Pat. No. 5,164,917 to Shichijo (the '917 patent), U.S. Pat. No. 5,026,659 to Lee (the '659 patent), U.S. Pat. No. 4,873,560 to Sunami et al. (the '560 patent), and U.S. Pat. No. 4,791,463 to Malhi (the '463 patent), disclose trench memory cells having a buried connection between the storage node diffusion of the transfer transistor and the storage node plate of the capacitor.
The memory cell described in the '463 patent has a single layer of polysilicon in the trench that is used for the storage node plate; the fixed electrode is formed in the single crystal silicon and there is no field shield. The capacitors of the memory cells described in the '887, '917, and '659 patents have inner and outer electrodes formed in the trench. The outer electrode of each of these capacitors is the storage electrode and is attached through the sidewall to the storage node diffusion of the transfer transistor. The trench capacitors described in the '463, '887, '917, and '659 patents also have no field shield. As for the capacitor described in the '560 patent, the inner capacitor electrode is attached via the sidewall of the trench to a buried storage node diffusion and the outer fixed electrode serves as a field shield. Like the field shield of the '502 patent, the field shield disclosed in the '560 patent is connected to a buried plate at the bottom of the trench.
The prior art describes techniques for solving the standby current problem discussed above by connecting the field shield to the substrate at the bottom of the trench. The prior art has failed to note the need for a field shield that can be connected at an arbitrary depth in the trench to a selected layer in the silicon so as to turn off vertical and horizontal parasitic transistors and gated diodes. Field shields attached to the substrate contacts at the bottom of the trench may address standby current, but they do not solve charge retention time problems.